With the advances of miniaturization in recent years, there is a growing tendency for semiconductor integrated circuits to be afforded with a higher degree of integration, greater scale and higher speed. The larger the scale of the circuit, the greater the skew of the clock signal that drives the circuit elements. To deal with this problem, it is now required that each functional block within a semiconductor integrated circuit be supplied with a clock signal of any desired timing.
A PLL (Phase-Locked Loop) or DLL (Delay-Locked Loop), etc., has long been used as a clock generating circuit for generating an internal clock of a semiconductor integrated circuit. Since control of such a feedback circuit is complicated, locking takes time (convergence time is long), the circuit is large in scale and power dissipation is high. For reference purposes, FIG. 7 illustrates the structure of a well-known ordinary PLL circuit. The PLL includes a phase comparator 101 for comparing the phase of an input clock signal and the phase of a frequency divider 106; a charge pump 102 for charging and discharging a capacitor based upon the output of the phase comparator 101 so as to output a voltage that conforms to the result of the phase comparison; a loop filter 103 for smoothing the output of the charge pump 102; a voltage-controlled oscillator (VCO) 104 for receiving the output of the charge pump 102 as a control voltage and varying oscillation frequency; a prescaler 105 for dividing the frequency of the oscillatory output clock of the VCO 104; and the frequency divider 106 for dividing the frequency of the output of prescaler 105. (There are also PLL arrangement that do not include the prescaler 105.) It should be noted that in a circuit capable of implementing fractional frequency division, for example, the frequency divider 106 is constituted by a pulse-swallow counter, etc., for varying the counting period (number of counts) based upon the output of the prescaler 105. The VCO 104 is constituted by a ring oscillator as obtained by connecting inverters (not shown) into a ring of odd-numbered stages, and transistor elements (not shown), whose bias voltage is varied based upon the control voltage so as to vary the output current, are inserted serially between each inverter and the power supply. By varying the driving current of the inverters that compose the ring oscillator based upon the control voltage, propagation delay time tpd (gain) is varied, whereby the oscillation frequency of the VCO 104 is controlled and changed.
By way of example, refer to the specification of Japanese Patent Kokai Publication No. JP-A-11-112309, which discloses a synchronous delay circuit (referred to as a “synchronous mirror delay”, or “SMD”) having a first delay circuit array (a measurement line) for measuring period or delay and a second delay circuit array (a replay line) for reproducing a measured delay. Further, the specifications of Japanese Patent Kokai Publication Nos. JP-A-10-303713 and JP-A-10-335994 disclose a clock frequency multiplier circuit that uses a synchronous delay circuit.
Refer to the specifications of Japanese Patent Kokai Publication Nos. JP-A-11-4145 and JP-P2002-163034A as examples of a clock frequency multiplier circuit that uses interpolators in which the phase of the output signal relative to the input signal is varied and controlled based upon a control signal. Japanese Patent Kokai Publication No. JP-A-11-4145 discloses a clock frequency multiplier circuit having a frequency divider, a plurality of interpolators (timing-difference splitting devices) the input to which is a frequency-divided clock, and a circuit for combining the outputs of the interpolators. In the circuits described in Japanese Patent Kokai Publication No. JP-A-11-4145, etc., weighting is applied by the interpolators and a logical operation is applied to generate a frequency-multiplied clock.
FIG. 8 is a diagram schematically illustrating the configuration of a clock multiplier circuit that employs a synchronous delay circuit having a first delay circuit array (a measurement line) 201 for measuring delay (clock period) and a second delay circuit array (a replay line) 202 for reproducing the measured delay, as well as a combinational circuit 203. The first delay circuit array 201 measures the input period, the second delay circuit 202 for reproducing delay creates timings of 1/N, 2/N, . . . of the input, and the combinational circuit 203 applies a prescribed logical operation to realize a desired frequency-multiplying number. FIG. 9 is a diagram useful in describing the timing operation of FIG. 8. In FIG. 9, IN1 represents a signal that is the result of frequency-dividing the input clock signal in a frequency divider 204 (frequency division by 4 in the example of FIG. 8), and IN2 represents a signal that is the result of delaying the signal IN1 by, e.g., one clock period in a delay element 205. The delay element 205 comprises a flip-flop that samples and outputs the frequency-divided clock signal of the frequency divider 204 at the rising edge of the input clock signal. In the example depicted in FIG. 9, the flip-flop constructing the delay element 205 of FIG. 8 outputs a signal, which is the inverse of the data signal, at the rising edge of the input clock signal.
The clock multiplier circuit using the interpolators described above has a number of problems.
The first problem is that the output is asynchronous with respect to the input clock signal. The cause of this problem resides in the fact that the operating time of the interpolators is irregular.
The second problem is that an error is produced in the duty of the output clock signal in dependence upon the precision of the interpolators.
Further, the clock multiplier circuit that uses the synchronous delay circuit illustrated in FIG. 8, etc., has the following problem shared with the clock multiplier circuit using the interpolators:
Specifically, the scale of the circuitry increases in proportion to the frequency-multiplying number. As multiplication becomes higher, the number of delay circuits or number of timing-difference circuits (interpolators) increases. As a consequence, generating a clock signal that is the result of a high degree of frequency multiplication is substantially impossible.